Uniting III-V tunnel FETs with silicon

22nd February 2017
Template-assisted selective epitaxy enables the construction of ultra-low power III-V TFETs on silicon substrates

Advances within the semiconductor industry have had a profound impact on the lives of all of us for more than 50 years. Industries as diverse as telecommunication, banking, consumer electronics, healthcare, and automotive have all benefitted from the adoption of electronic devices and information technology. This has revolutionized how we work, while re-shaping our society.

The driving force behind these significant changes has been the dramatic increase in integration density, made possible by shrinking the MOSFET. Packing smaller transistors closer together has slashed the manufacturing costs in a manner predicted by Gordon Moore back in 1965 (also known as Moore’s law), and equipped end-costumers with ever increasing functionality at ever lower prices.

Unfortunately, as device dimensions have scaled, passive and dynamic power consumption has not kept pace. This has meant that reductions in supply voltage (VDD) have lagged behind the rate of miniaturization at advanced technology nodes. Even for an ideal MOSFET, the off-state current (Ioff) increases ten-fold when VDD is reduced by 60 mV and the threshold voltage (Vth) is lowered accordingly (see Figure 1). This inherent weakness cannot be addressed by changes in material or device geometry, as it is associated with the inverse subthreshold slope (SS) of the MOSFET, which cannot be less than 60 mV/decade at room temperature, due to thermionic emission of electrons over a potential barrier.

Figure 1. Typical transfer characteristics (IDVG) for a MOSFET (red) and a TFET (green). An ideal switch (blue) would provide the highest on-state current at the smallest gate voltage (VGS) and a large on/off ratio. The inverse subthreshold swing (SS) of a MOSFET is limited to 60 mV/dec, which precludes operation at voltages below 0.5 V. In contrast, in a TFET, the SS can be smaller, enabling the decrease of the supply voltage VDD and the dynamic power consumption. In addition, the energy filtering effect in a TFET allows a further reduction of Ioff compared with the MOSFET, which substantially reduces static power consumption. 

To overcome the 60 mV/decade limit, developers of next-generation transistors are exploring novel devices that are based on different physical mechanisms. One of the most promising architectures is the tunnel FET: it resembles the MOSFET, but does not rely on thermionic emission [1]. Instead, carriers are injected into the channel via quantum-mechanical, band-to-band tunneling (BTBT).

With a TFET, BTBT acts as an energy filter, ensuring that only carriers within a certain energy range contribute to the conduction of current. With hot carriers filtered out, the steep-slope SS is no longer barred from plunging below the thermal limit of 60 mV/dec. What’s more, as the TFET can operate below a VDD of 0.5 V, and the passive power is proportional to VDD and the off-current, a device’s power consumption could plummet by a factor of 100.

The TFET consists of a p-i-n reverse-biased diode, with a gate overlapping the intrinsic region (see Figure 2). This device can be formed from one or more materials, and ideally it should deliver a high on-state current Ion, because this reduces the delay time constant RC of the circuit and therefore increases the operating frequency.

Figure 2. A p-type TFET, and a corresponding band diagram. In this case, the source voltage (VS) is fixed to ground (GND), whereas the negative drain voltage VD determines a reverse-bias operation. The gate voltage (VG) shifts the channel bands downwards (off-state) or upwards (on-state), respectively blocking or enabling the band-to-band tunnelling current (blue-shaded area). The band alignment in the TFET is responsible for the energy-filtering mechanism that effectively cuts off the high-energy tail of the source Fermi function (EFS) and enables a subthreshold swing of below 60 mV/decade.

Producing a high Ion is not easy, however, because it depends on the tunneling probability (in contrast, for a MOSFET, ID is proportional to the applied gate bias). To produce a higher Ion, materials with smaller bandgaps and lower effective masses should be used, as they provide higher tunneling probabilities; and direct bandgap materials should be selected, as they reduce interactions between charge carriers and phonons. Silicon is far from ideal, because it has a large effective mass, and its indirect bandgap leads to a lower tunneling probability, due to interactions between charge carriers and phonons. 

The case for III-Vs
Turning to III-V materials for the construction of TFETs is very appealing. It provides the opportunity to use direct bandgap materials with low bandgaps and small effective masses. Furthermore, lattice matched III-V heterostructures allow the engineering of tunnel junctions with large tunnel currents. Note that to obtain a complementary logic similar to that of an n-MOSFET/p-MOSFET, band alignment for the TFETs must be designed for p-type conduction or n-type conduction. 

At IBM Research, Zurich, we are developing this class of TFET. We are pursuing the pairing of InAs and silicon for the p-type device, and the combination of InAs and GaSb for the n-type cousin. The former has the smallest tunneling bandgap for holes in a staggered band alignment, whereas the latter exhibits very high electron tunneling rates in a broken-gap configuration.

One of the challenges of this approach is that it demands the integration of different materials. And in order to be economically viable, the III-V-based TFET technology must be integrated on a standard CMOS-compatible substrate.

To address these challenges, we have been developing a method for integrating III-Vs on silicon, along with a compatible process flow for p- and n-type devices.

Integrating III-Vs with silicon is very challenging, due to the significant lattice mismatch between the two materials. This difference in atomic spacing gives rise to interfacial defects, which can eventually propagate through the entire crystal and degrade electrical performance.

To address this issue, there have been attempts to integrate III-Vs with silicon using various technologies, including metamorphic buffers, wafer bonding, epitaxial lateral overgrowth, aspect-ratio trapping and selective area growth. However, all these approaches are afflicted with at least one of the four following weaknesses: exorbitant fabrication costs, unsatisfactory crystal quality, a process that is unsuitable for scaling, and a process that is not capable of integrating III-Vs with the (100) orientation of the silicon substrate.

In stark contrast, our new technology – template-assisted selective epitaxy (TASE) – is unimpeded by any of those four issues, and enables the integration of dislocation-free III-V crystals on silicon (100).Key steps in our process include: the definition of a sacrificial silicon layer on either a bulk silicon (100) or silicon-on-insulator (SOI) substrate; the formation of a SiO2 template around the silicon; and the etching of the template at one side and of the sacrificial layer, to leave an empty tube and a silicon seed for III-V growth by MOCVD (see Figure 3 for an outline of the process, and [2],[3] and [4] for more details). 

Figure 3. Templated-assisted selective epitaxy can form a lateral InAs/silicon hetero-junction (details are given in [3,5]). The silicon segment (green) inside the SiO2 template (light blue) defines the seed for selective MOCVD growth of III-V material, such as InAs (dark blue). The heterojunction that is created lies on a buried oxide that electrically isolates the device from the substrate.

A noteworthy element of our technology is the nucleation of the III-V crystal on a small silicon seed, which yields a material with a high crystal quality. Subsequent growth is confined inside the template that defines also the device geometry. These attributes are highly valued for TFETs, because the crystal quality of the heterojunction strongly affects the tunneling current. Device performance gets an additional boost from the growth of III-Vs on a buried oxide of SiO2, which electrically isolates the devices and reduces leakage-current paths through the silicon substrate.

Our TASE technology is suitable for the fabrication of InAs and GaSb nanowires, which can be very closely packed to each other (see Figure 4). The InAs nanowires were grown first, before adjacent channels were filled with GaSb.  Note that our technology is not limited to the integration of III-V TFETs – its great versatility allows it to be applied to other III-V devices, including MOSFETs, photodetectors, LEDs, and lasers. Thanks to this, it is possible to form a variety of devices on a single chip, all positioned at their desired location.

Figure 4. InAs (blue) and GaSb (pink) nanowires grown by MOCVD with a spacing of less than 200 nm between them, including the silicon nucleation seed (green). Using templated-assisted selective epitaxy, it is possible to obtain a very tight integration density of diverse III-V materials and devices for increased on-chip functionality.

Fabrication of our TFETs continues with the definition of a pair of high-k dielectrics, Al2O3 and HfO2, and the addition of metal gates made from either TiN or tungsten. Afterwards, spacer and metal contacts for source and drain regions are defined for both polarity devices.

High-k dielectrics are used in our TFETs, because they provide excellent charge coupling to the channel, thereby improving electrostatics and the sub-threshold slope. However, care must be taken to avoid a degradation of the sub-threshold slope through interface traps, which can be formed during the deposition of high-k materials on III-Vs.

The narrowness of our silicon, InAs and GaSb nanowires highlights the potential of our TASE technology. Cross-section areas as small as 17 nm x 27 nm and 25 nm x 35 nm have been obtained for the p-TFET and n-TFET (see Figure 5). These devices are the first demonstration of a complementary III-V heterostructure TFET technology on silicon that yields transistors at relevant technological nodes, and employs a lateral orientation that is compatible with the state-of-the-art CMOS fabrication line. We have evaluated the performances of our p- and n-TFETs at a range of temperatures, using a standard four-probe electrical setup. Transfer characteristics were determined at a source-drain bias of 0.5 V (see Figure 6). For both devices gate leakage current is negligible, and does not affect the characteristics (not shown here, see [5]).

Figure 5. A 2 cm x 2 cm chip containing TFETs fabricated by templated-assisted selective epitaxy, and a corresponding false-coloured top-view scanning electron microscopy image of p-type (bottom left) and n-type (bottom right) devices. For simplicity, p- and n-TFETs have been implemented on two different wafers, but as shown in Figure 4, the processes are compatible. The dimensions achieved are 17 nm x 27 nm and 25 nm x 35 nm for p- and n-TFETs, respectively.

The InAs/silicon p-TFET exhibits excellent performance, with a large on-off ratio of 106, an Ion of few mA/mm, and a SS that falls from about 70-80mV/dec at room temperature to 50 mV/dec at 125K. The SS improvement with cooling occurs because a fraction of the traps present at the InAs/silicon heterojunction are frozen out, leading to a trimming of the trap-assisted tunneling current. 

Our InAs/GaSb n-TFET also exhibit an improvement in SS at lower temperatures. However, BTBT is inhibited by the presence of traps at the hetero-junction, which prevent the SS dropping below 60 mV/dec [6,7]. We aim to address this by reducing the number of traps at the heterojunctions and the high-k/III-Vs interfaces.

Figure 6. Temperature-dependence characteristics of p-TFETs (left) and n-TFETs (right).  The subthreshold swing improves at lower temperatures, because traps at the heterojunction and at the high-k/III-V interfaces are frozen out.

Following more than 50 years of integration technology that has revolved around the silicon MOSFET, our work, along with that of some of our peers, shows that there is the possibility of a new form of transistor for low-power applications. There are many challenges that still need to be overcome, but this development will bring hope to engineers that need to build ultra-low power circuits for the likes of the Internet-of-Things (IoT) market. 

In this particular market, numerous devices will collect and transmit large amounts of data simultaneously. This will be partially analyzed on the chip, and further in the cloud. However, a major concern surrounding the IoT is the power consumption of the electronics. Energy harvesting to power sensors in buildings would allow power to be distributed efficiently and wirelessly to where it is needed. Still, the power consumption of the electronics on chip should be as low as possible to enable real-time communication among devices. For these requirements, TFETs could have an edge over the so far most successful device concept, the MOSFET. 

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