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Big III-V nanowire wafers go into production

June 12, 2013
InAsP (indium arsenide phosphide) nanowires grown on a silicon substrate open up many possilbilities
Researchers have developed a large-scale hetero-epitaxial growth process of III-V nanowires on a silicon (Si) wafer.

The team who created the process are from Ulsan National Institute of Science and Technology (UNIST), South Korea, and University of Illinois, U.S.A.

The scientists demonstrated a novel method to epitaxially synthesise structurally and compositionally homogeneous and spatially uniform ternary InAsyP1-y nanowire on silicon at wafer-scale using MOCVD. The high quality of the nanowires is reflected in the remarkably narrow PL and X-ray peak width and extremely low ideality factor in the InAsyP1-y nanowire/silicon diode.
A nanowire is a nanostructure with a diameter of the order of a nanometre (10-9 metres). Alternatively, nanowires can be defined as structures that have a thickness or diameter constrained to tens of nanometres or less and an unconstrained length. Technology related to nanowires has been selected as one of the 10 Breakthrough Technologies of 2004 by MIT Technology Review.



Optical and SEM images of the InAsyP1-y nanowire array

High-aspect-ratio semiconductors have led to significant breakthroughs in conventional electrical, optical, and energy harvesting devices. Among such structures, III-V semiconductor nanowires offer unique properties arising from their high electron mobility and absorption coefficients, as well as their direct band gaps.

A common technique for creating a nanowire is Vapour-Liquid-Solid (VLS) synthesis. This process can produce crystalline nanowires of some semiconductor materials. However, metal catalysts, usually expensive noble metals, should be used for initiating the VLS mechanism.

What's more, these metal catalysts are known to significantly degrade the quality of semiconductor nanowires by creating deep levels, thus limiting practical applications of nanowires into optoelectronic devices.

In this work, however, Choi’s group developed a novel technique of growing III-V semiconductor nanowires without metal catalysts or nano-patterning. Aixtron's A200 reactor was used for the growth of the InAsyP1-y layer.
Then, the wafer was immediately dipped in poly-L-lysine solution (Sigma-Aldrich inc.) for 3 minutes then rinsed in DI water for 10 seconds. The silicon substrate was then loaded into the MOCVD reactor without any delay. The reactor pressure was lowered to 50 mbar with 15litre/min of hydrogen gas flow. Then the reactor was heated to growth temperatures (570 – 630 ℃), and stabilised for 10 minutes.

A 2 inch Si (111) wafer was cleaned with buffer oxide and etched for 1 minute and immersed in deionized (DI) water for 2 seconds.

SEM micrograph (top) and electrical characterisation graphs of the hetero-junction solar cells composed of n- InAs0.7 P0.3 nanowire array on p-Si (111) substrate (bottom)

“If we develop new technology which manages the density of nanowire and band gap energy with further study, it is also possible to produce high-efficiency & low-cost large scale solar cells,” says Choi. “This technology will give us a chance to lead the research on the new renewable energy.”

This work was supported by the Future-based Technology Development Program (Nano Fields) through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology.

This research was published on the web on May 7th in the paper:" Wafer-Scale Production of Uniform InAsyP1-y Nanowire Array on Silicon for Heterogeneous Integration" by Jae Cheol Shin et al, in ACS Nano, DOI: 10.1021/nn4014774

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