By Paula Doe, SEMI
To advance the performance of power and RF devices, new packaging technologies are required to address the parasitic roadblock.
The $2 billion predicted market for compound semiconductor devices beyond LEDs by 2020 depends largely on solutions for managing the parasitics and the heat dissipation with new packaging technology.
“What’s needed now for power devices are innovations in the packaging technology to best take advantage of the compound semiconductor properties. The chip can work at 250°C, but the typical silicon packaging doesn’t work at more than 150°C,” notes Philippe Roussel, leader of the compound semiconductor business at analyst firm Yole Développement, who will speak at the program on these manufacturing issues at SEMICON West 2014 (www.semiconwest.org) in San Francisco in July.
“The real action is on the packaging side,” adds Roussel, “where material and chemical suppliers are pushing like crazy to develop high temperature solutions with new gels, polymers and cooling systems.”
It’s a similar story for compound semiconductor RF devices in the mobile front end.
“Important for the near future—and people tend to underestimate this—are advances in packaging technology,” suggests Thomas Meier, TriQuint VP of Central Engineering, who is also speaking at SEMICON West.
“With the tremendous pressure to reduce dimensions in the x, y and z directions of the multichip modules overmolded on multilayer laminate, we need major improvements in line accuracy, width, and alignment, as well as heat spreaders and embedded die, and of course no one wants to pay a single cent more.”
Wide-band-gap devices will need new variants of flip chip, new substrate materials, new bonding materials
“The biggest need to enable wide-band-gap (WBG) devices is for efficient, low-cost multi-chip packaging,” concurs Sameer Pendharkar, Texas Instruments power device and wide-band-gap roadmap manager and TI Fellow.
While these devices offer high-speed switching of high voltage, the technology does not allow large-scale integration. This means that WBG power devices need to be supported by silicon drivers and controllers, and the parasitics between the silicon driver and WBG power device need to be minimized for high-speed switching.
According to Pendharkar, one promising option is multi-chip, flip chip packaging, where the driver and the FET can be co-packaged to minimize parasitics. These packages will need to be thin for efficient thermal capability, and have both top side and bottom side cooling. Multiple components with different substrate potentials may need isolated package substrates that are electrically isolating but thermally conducting. Electromigration in the high current devices would need to be addressed through properly-sized interconnects and substrate layout.
New approaches will be needed to avoid the impact of parasitics and to manage the heat dissipation. “The wire bond, for example, is like an antenna creating all sorts of problems with parasitic inductances,” says Fraunhofer IZM director Klaus-Dieter Lang. That means variants of flip chip or copper pillar packaging, or even sandwich-style direct copper-to-copper connections will be needed, but with improved materials, better understanding of the interface characteristics, and much tighter tolerances to prevent misoperation or damage. Substrate materials, and the design and positioning of the components on the substrate, are also all important to reduce parasitics, and very different from what’s needed for standard silicon components, he notes.
New substrate materials must also serve to improve heat dissipation. While various ceramic and metal materials are under consideration, one intriguing possibility is to use advanced printed circuit board laminate with thicker metal layers. Lang says Fraunhofer IZM has some promising results with embedding the power devices and passives into cavities in the PCB, and using the copper layers of the laminate for interconnection and heat management.
From the reliability point of view, new kinds of solder or bonding materials will be needed as well. “The next technology to be implemented, in my opinion, will be silver sintering or diffusion soldering for die bonding,” says Lang. Copper wire interconnect is also a possibility for higher reliability under thermal cycling load because of higher fatigue strength, lower CTE and much better thermal conductivity of copper. Other options for new thermal interface materials include nano fillers, or even carbon nanotubes or diamond films.
These speakers will be joined by Marina Sofas, technology manager of the new US Dept. of Energy Wide-Band-Gap device manufacturing research program; Primit Parikh, president and co-founder of Transphorm; and Frank Burkeen, VP&GM of KLA-Tencor’s Candela division in discussing what’s needed next to move these emerging compound semiconductor devices to volume markets, at SEMICON West 2014 (www.semiconwest.org),July 8-10, in San Francisco. Progress on integrating compound semiconductors with silicon will also be covered in the silicon photonics program.