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Simulations enhance the development of power devices
Nov 24, 2011
Simulations hold the key to unlocking the potential of wideband gap semiconductor transistors with novel architectures, say Hugh Wong, Nelson Braga, Shiyang Tian and Ricardo Borges from Synopsys.
Growing interest in greener forms of electricity generation and fuel efficient vehicles is spurring the development of a new breed of power electronic system. In turn, this is creating new opportunities for the semiconductor power device technologies lying at the heart of most of these systems.

Examples of such activities include increased efforts to harness the power of the sun and wind, which have motivated the development of more efficient inverters. Similarly, future power grids will require new powerswitching and flow-control technologies to manage and distribute increasingly diverse energy sources, including renewables with seasonal and diurnal variation. And in transportation, it is possible to increase the driving range of hybrid and electric vehicles with more efficient inverters and converters that can operate at a higher temperature, require less cooling, and enable a reduction in the weight of the car.

Silicon power devices are dominant in today’s power electronics and they will continue to evolve. However, wide bandgap alternatives based on SiC and GaN are now starting to fulfil their long-held promise for highpower, high-temperature applications, and they are gaining traction in applications beyond the performance envelope of silicon.

At a given breakdown voltage, silicon is inferior to both SiC and GaN in terms of on-resistance, which is a key figure of merit in power switching applications. In the case of SiC, whether used as a device technology or as a substrate for GaN devices, its higher thermal conductivity improves heat dissipation. What’s more, in SiC and GaN, the low intrinsic carrier concentration resulting from the large energy gap allows device operation at higher junction temperatures. Both effects simplify heat sink design and cooling systems and could unleash a range of products setting new benchmarks for affordability, size and weight.

Recently, an increasing interest in GaN and SiC has spawned many new device designs that – when combined with improved processing techniques, higher quality SiC substrates, and lower-defect GaN heteroepitaxy – have led to promising demonstration devices. But there remains a strong impetus for further optimisation of device design and the tailoring of device characteristics to a wide range of applications.

One tool that engineers can use to develop novel device structures and exploit the benefits of wide bandgap semiconductors to the full is technology computer-aided design (TCAD). At Synopsys, which is based in Mountain View, CA, we have developed software capable of doing precisely that – the Sentaurus Device simulator. In this article we illustrate the capability of this tool through simulations of a normally off GaN HFET and a SiC insulated-gate bipolar transistor (IGBT) designed to meet low loss power switching applications.

Simulating GaN and SiC devices presents a set of challenges that are not faced when working with more common semiconductors, such as silicon and GaAs. One of these is the vast range of values for some of the characteristics associated with wide bandgap materials. For example, the intrinsic carrier concentration innate in GaN and SiC is incredibly low, but the doping levels of contact and cap layers can be very high. For accurate simulation of leakage currents and the onset of avalanche breakdown, the simulator must be capable of numerically resolving 25 or more orders of magnitude.

Recent versions of Sentaurus Device address this issue through extended precision arithmetic, which improves the relative accuracy of the numerical resolution.

Normal 64-bit floating-point representation has a relative accuracy of 2.22 x 10-16. 80-bit extended precision arithmetic, which is supported in hardware with no noticeable degradation in performance, has a relative accuracy of 1.08 x 10-19. In contrast, moving up to 128-bit and 256-bit improves the relative accuracy to 4.93 x 10-32 and 1.22 x 10-63, respectively, but at the expense of longer simulation time.

Catering for crystallinity…

Simulations of wide bandgap power devices must alsocater for intrinsic properties specific to each material.Except for its cubic 3C polytype that has limitedcommercial application, all polytypes of SiC havehexagonal crystal structures. Consequently, anisotropyfeatures in many important physical parameters –mobility, impact ionization, thermal conductivity,effective mass and electrical permittivity.

What’s more, doping techniques employed for SiC can also differ from those used for other semiconductors. Insitu doping of epitaxial layers is common, especially for low-doped regions, but ion implantation is gaining popularity in modern SiC devices. Here, too, the technology differs from silicon.

In SiC, ion implantation tends to be carried out at a high temperature to activate the dopants during the implant. Fortunately, models for ion implantation in SiC have substantially improved over the years, and our latest simulation tool accounts for wafer off-axis angle and temperature. Thanks to these refinements, our simulations of dopant concentration are a good match to real data (see Figure 1). We are also currently working at modelling other SiC processes, including oxidation, where different growth rates and interfacial fluxes occur for the silicon and carbon faces, and dopant diffusion takes place at very high temperatures. We detailed our calibration of SiC physical models applied to TCAD simulations three years ago in this magazine (see Compound Semiconductor, October 2008, p 31).

 



Figure 1. 4H-SiC on-axis, 60 keV, aluminium implant at doses (0.63, 1.3, 3.4, 4.9) x 1012 cm-2. Since the implant is performed on an on-axis wafer, deep channelling tails are created - their close match to the experimental SIMS profile attests to the accuracy of the Monte Carlo implant model

…and polarization

In GaN devices – particularly HFETs, where a twodimensionalelectron gas functions as the conductionchannel – it is paramount that models handlepolarization effects. The polarized wurtzite crystalstructures of AlGaN, InGaN and GaN have dipolesacross the crystal in the [0001] direction that lead tospontaneous (pyroelectric) polarization. In addition,there is strain-induced (piezoelectric) polarization in III-Ndevices incorporating pseudomorphic  heterostructures.The primary effect of these sources of polarization is thecreation of an interface charge, which is due to abruptvariations in the polarization at the AlGaN-GaNheterointerface and at the AlGaN surface. We computethis interface charge with a built-in polarization modelthat accounts for spontaneous and piezoelectriccomponents.

More recently, Jesús del Alamo’s group from MIT has reported degradation in GaN-based HFETs and postulated a link with the converse piezoelectric effect. High electric fields develop near the drain side of the gate, leading to strain relaxation through formation of mechanical defects and, consequently, the generation of electrical traps. When negatively charged, these traps cut drive currents, shift the threshold voltage positively, and increase drain access resistance. We believe that simulations can help to optimise the device design to mitigate these deleterious effects because they enable visualization of the spatial distribution of converse piezoelectric fields when the transistor is stressed.

Early efforts to develop GaN HEMTs focussed on physical characterization of trapping effects and ways to mitigate them. These traps hampered device commercialisation for many years, so it is of no surprise that early TCAD simulations focused on providing insights into the bulk and surface trapping behaviour to guide process improvements. Such efforts paid dividends, revealing the benefits of limiting carbon impurities in buffer layers and showing ways to optimise the device structure to suppress operational conditions conducive to trapping.

An important illustration of these early efforts was a simulation by us of the impact of field plates on the electron temperature in the channel. This study, which we detailed in Compound Semiconductor in 2006 (July edition, p 17), showed that field plates can reduce the electric field at the drain-edge of the gate, contributing to a reduction of the electron temperature and trapping. If a plate is not in place, hot electrons diffuse into the bulk, where they became trapped. Insert a field plate and trapping falls, due to a lowering of electron temperature that limits electron spillover from the channel into the bulk. Our gate-lag transient simulations revealed key insights into the so-called current collapse phenomena, with the addition of field plates aiding the recovery of the drain current following a gate off-on switching pulse.

Thanks to improvements in epitaxial material and processing, devices now exhibit nearly ideal characteristics. Although extensive reliability studies of GaN devices are still underway, the nitride community has entered a phase in which simulation of their devices takes on a more conventional role: It provides a tool for designing and optimising device structures for specific applications.

For power switching, gate-drive circuitry is greatly simplified if the switching FET operates in enhancement mode, because the device is then normally off. Interest in this class of device has recently taken off, because it has tremendous commercial potential for power switching.

One interesting and promising variant of the normally off nitride transistor is the p-type GaN gate device that has been pioneered by Oliver Hilt and co-workers from the Ferdinand-Braun-Institute in Leibniz, Germany. As the paper presented by this group at last year’s International Symposium on Power Semiconductor Devices and ICs did not report some of the key dimensions of their transistors, we have had to adopt reasonable assumptions to create a structure consistent with the device performance results (see Figure 2 for details).

 



Figure 2. A crosssection of the simulated HEMT structure (gate region)

In this p-type gate device, highly doped regions are created under the source–drain electrodes that stretch down to the GaN channel to emulate metal spikes and to control contact resistance. Magnesium-doped GaN is used as the p+ gate to deplete the channel at Vg=0, yielding a normally off transistor. An AlGaN buffer is used to increase the threshold voltage, and increasing the aluminium content in this layer reduces the onresistance.

We assume that the Al0.05Ga0.95N buffer is completely relaxed, and the subsequent channel and barrier layers are strained to match the lattice constant of Al0.05Ga0.95N, but with 20 percent of relaxation. The large polarization divergence at the AlGaN barrier surface (barrier/nitride interface) produces a large sheet of negative polarization charge. One might expect holes to accumulate at that interface and completely deplete the channel of electrons. However, in reality it is still not clear whether the polarization charge is compensated by fixed charges or interface trap states. According to our simulations, accumulated holes at the surface of the AlGaN barrier are completely compensated by deep, single-level trap states.

 



Figure 3. Off-state leakage curve for device with 8 μm field plate and 18 μm gatedrain spacing

 

To assess the device performance for power-switching applications, we perform voltage sweeps of Id-Vg, Id-Vd and off-state breakdown voltage. To match the subthreshold slope of the Id-Vg curve reported by Hilt and his co-workers, we add traps to the AlGaN barrier/GaN channel interface. As expected, our simulations reveal that the off-state leakage current and breakdown  voltage are strongly influenced by the passivation nitride thickness and field-plate length. What’s more, traps in the buffer affect both the sub-threshold slope and off- state leakage current. Our simulations employ Schottky contacts for the source and drain. Electron tunnelling is turned on and the electron tunnelling mass is made to be arbitrarily small so the contact is essentially ohmic. Taking this approach improves convergence and avoids abrupt band bending near the contacts. The tunnelling mass can also be used to tune the contact resistance.

The simulations that we have performed reveal that a breakdown voltage in excess of 600 V is possible for a HFET with an 8 μm field plate and gate-drain spacing  of 18 μm – such a device promises to make a commercial impact on the power device market (see Figure 3 for a plot of the off-state leakage curve). A similar structure with a 1.8 μm field plate had good gate control at a drain voltage of 15 V (see Figure 4), and exhibits negative output conductance due to selfheating (see Figure 5).

 



Figure 4. Id-Vg and Ig-Vg curves for a structure with a 1.8 μm field plate and 6 μm gatedrain spacing, biased at Vd=15V

 



Figure 5. Id-Vd curves for structure with a 1.8 μm field plate and 6 μm gatedrain spacing. The negative output conductance shown in the top trace is due to selfheating

SiC IGBTs

In the power industry, the silicon IGBT is widely used,thanks to its combination of a very low on stateresistance and superior on-state current density at highvoltages. These attributes also hold for SiC equivalentsthat promise to increase operating voltage range.

We have performed three-dimensional simulations with a 4 μm by 4 μm domain over a trench SiC IGBT amenable to current SiC process technology (see Figure 6 for details of the device architecture). Due to the relatively low doping level of just 6 x 1014cm-3 in this long drift region of about 160 μm, very high breakdown voltage is expected.

 



Figure 6. The meshed n-type SiC  IGBT with n+ polysilicon gate and 50 nm SiO2 gate insulator. For clarity, middle portion of the drift region is truncated

 

Simulations re-enforce this expectation, suggesting that the breakdown voltage should exceed 12 kV (see Figure 7). To perform this simulation, we turned to extended precision arithmetic (80-bit) to resolve the extremely small off-stage leakage current that is present before the onset of avalanche breakdown.

 

Figure 7. The n-type SiC IGBT has an incredibly high breakdown voltage. This curve also catches snapback, a sudden lowering of the device internal resistance as the collector current increases. The initiation of the avalanche breakdown at the bottom corner of the trench is captured in the inset

As GaN and SiC devices gain market traction and target a growing array of applications, simulation will play an ever-increasing role in fully exploiting the excellent set of attributes of these wide bandgap materials. The design of power devices has many degrees of freedom, opening the way to radical device structures and the optimisation of current designs, all of which are well supported by simulation.

In the future, modelling of fabrication process in SiC and GaN technology will become more important, as not only structural details but also process conditions will be subject to optimisation. And since the performance of power modules is tightly coupled to the performance of the discrete power devices assembled in the module, simulation efforts allowing the co-design of devices and modules will see the use of TCAD data in the characterization of behavioural models for circuit and system-level design.

© 2011 Angel Business Communications. Permission required.

FURTHER READING J. Joh and J. A. del Alamo, IEDM Tech. Dig 415 (2006) O. Hilt et al., Proc. ISPSD 347 (2010)
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